Research
Four processor generations. Four open-access papers. FPGA validated on AWS F2 and Kria K26.
N4
Coming soon512-core dual-chiplet architecture. 4.19 million physical neurons, 134 million virtual via TDM. FPGA validated on AWS F2 at 62.5 MHz. Edge variant validated on Kria K26 at 0.378 W total board power.
N4-Edge
Low-power embedded variant. SRAM-only, no HBM. Targets $5-20 FPGA modules.
Architecture evolution
Each generation extends the ISA and adds hardware capabilities. N1 through N3 have dedicated product pages with full specifications.
| N1 | N2 | N3 | N4 | |
|---|---|---|---|---|
| Cores | 128 | 128 | 128 (16 tiles) | 512 (dual chiplet) |
| Neurons | 131K | 131K | 524K–1M | 4.19M (134M virtual) |
| Neuron models | 1 (CUBA LIF) | 5 | 7+ (programmable) | 8 (50-opcode microcode) |
| Neuron engine | Fixed datapath | Microcode | Microcode + ANN mode | Microcode + ANN/SNN hybrid |
| Weight precision | 8-bit fixed | 1–16-bit variable | 1–16-bit variable | 1–16-bit variable |
| Spike formats | Binary | Binary + graded | Binary + graded + compressed | Binary + graded + compressed |
| Learning | STDP + reward | 3-factor + homeostatic | Per-tile, 28-opcode ISA | 50-opcode, per-core |
| Synapse formats | 3 | 4 | 4 + compression | 10 |
| Memory | 1 level | 1 level | 4 levels (L1–L4) | HBM3E 48 GB, 2.0 TB/s |
| Virtualization | — | — | NeurOS (680+ networks) | NeurOS v2 |
| FPGA validated | VU47P (16-core) | VU47P (28 tests) | F2 + K26 | F2 + K26 |
| ASIC projection | — | 19–38 mW (28 nm) | — | 100–300 mW (28 nm) |
FPGA validation
All four generations validated on physical FPGA fabric. RTL on hardware at clock speed, compared bit-exact against a CPU reference simulator. Covers neuron dynamics, synaptic formats, mesh routing, on-chip learning, microcode execution, and state isolation.
Benchmarks
Standard neuromorphic benchmark suite. SHD, SSC, N-MNIST, DVS Gesture. Results reported alongside current state-of-the-art. The architecture is competitive on SHD (91.0% vs 96.4% SOTA). The gap is in training methodology, not hardware capability.
Loihi 2 parity audit
155 features identified in Intel's Loihi 2 architecture. Each mapped to the N2 implementation and verified against RTL, SDK, and test suite. 152 fully implemented. 3 require physical I/O pins not present on FPGA dev boards. 0 missing.
Publications
Catalyst N4: A 512-Core Dual-Chiplet Neuromorphic Processor with 134M Virtual Neurons, Spike Tensor Core, and Hardware Neuroscience Primitives
512 cores, 134M virtual neurons via TDM, 16x16 Spike Tensor Core, 8-head spiking attention, KV cache, hyperdimensional computing, Hopfield memory, hardware backpropagation, federated learning, post-quantum security, RV64GC with 14 custom opcodes.
DOI 10.5281/zenodo.19332513Catalyst N3: A 128-Core Hybrid Neuromorphic Processor with Hardware Virtualisation, Per-Tile Learning, and Silicon Metaplasticity
128 cores, 16 tiles, NeurOS virtualisation (680+ concurrent networks), ANN/SNN hybrid mode, 4-level memory hierarchy, per-tile 28-opcode learning ISA, silicon metaplasticity.
DOI 10.5281/zenodo.18881283Catalyst N2: Full Loihi 2 Parity in an Open Neuromorphic Architecture
155-feature Loihi 2 parity audit, 5 neuron models, programmable microcode engine, 3-factor learning with homeostatic plasticity, graded spike payloads.
DOI 10.5281/zenodo.18728256Catalyst N1: A 131K-Neuron Open Neuromorphic Processor with Programmable Synaptic Plasticity
128 cores, 131,072 CUBA LIF neurons, STDP + reward-modulated plasticity, 14-opcode learning ISA, SHD 90.6%.
DOI 10.5281/zenodo.18727094Software
The SDK includes three execution backends. The CPU backend is the reference implementation. Every commit is tested against all three.