Catalyst N1

128-core neuromorphic processor. Open hardware.

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What takes a billion-dollar lab and a hundred engineers, we built from scratch. Then open-sourced it.

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Cores
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Neurons
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Synapses / core
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SHD benchmark
Architecture

128 cores. One mesh.

Each core: 1,024 spiking neurons, 131K synapses, a programmable learning engine. Cores communicate through a barrier-synchronized mesh or asynchronous event-driven network-on-chip.

SPIKE MESH ROUTER Core 0 Neurons 1024 LIF CSR 131K syn Learning 14-op ISA Delay 0–63 step Core 1 Neurons 1024 LIF CSR 131K syn Learning 14-op ISA Delay 0–63 step Core 2 1024 LIF 131K syn 14-op ISA 0–63 step ··· × 128 cores DENDRITIC TREE 4 compartments / neuron GRADED SPIKES 8-bit payload per spike GALS ASYNC Event-driven operation HOST INTERFACE · UART · 9 COMMANDS Catalyst N1 · 32,768 neurons · CERN-OHL-W
Δt (ms) Δw -50 -25 0 +25 +50 LTP LTD Spike-Timing Dependent Plasticity · 3-Factor with Eligibility
Learning

It learns on its own.

Three-factor plasticity with eligibility traces and reward modulation. A programmable microcode engine lets you write custom learning rules — STDP, reinforcement learning, homeostatic normalization — in 14 opcodes.

SDK

Python to silicon.

Define networks, compile to hardware, simulate or deploy. Cycle-accurate simulator for development. FPGA backend for the real thing.

import neurocore as nc
net = nc.Network()
exc = net.population(64, params={"threshold": 800})
inh = net.population(16, params={"threshold": 600})
net.connect(exc, exc, topology="random_sparse", p=0.1)
net.connect(exc, inh, topology="all_to_all", weight=150)
net.connect(inh, exc, topology="all_to_all", weight=-300)
sim = nc.Simulator()
result = sim.run(timesteps=100)
result.raster_plot()
How it compares
Catalyst N1Loihi 1TrueNorthSpiNNakerBrainScaleS
Total neurons131K131K1M18K*512
Synapses/core131K128K256SW224
On-chip learningYesYes—YesYes
Graded spikesYes————
Dendrite treesYesYes———
Embedded CPUYesYes—Yes—
Open designYes——Yes—

*Per ARM968 core. SpiNNaker scales to ~1M neurons across 1000+ chips.

Built by

Henry Shulayev Barnes

Independent hardware engineer, UK. Every line of RTL, every test, every tool in the SDK. One person. 25 development phases. 98 test scenarios. Zero failures.

Open source

See everything.

Full RTL, testbenches, SDK, and paper. CERN-OHL-W licensed. No NDAs. No black boxes.

View repository
In development

Catalyst N2

Next generation. Higher neuron density, enhanced compute primitives. Targeting feature parity with the industry's latest.

Get in touch.

Collaboration, licensing, or early access.

[email protected]